The semiconductor memory integrated circuit, for example, the dynamic random, access memory (DRAM), generally adopts input buffer means at the input end of the address latch for buffering the input address signal. The address latch is provided with the input buffer to obtain sufficient noise margin for rejecting noise, and fast processing speed. Moreover, the input buffer should ensure the normal function of the address latch and the reliability thereof in case of an input signal having excessive voltage. In other words, the function of the input buffer means is to ensure the performance of the address latch for high-voltage and high-speed input signals.
The conventional input buffer means is generally connected to an external voltage source E.sub.VCC to increase the allowable range of input signal levels. FIG. 1 shows the block diagram of a conventional input buffer means for an address latch in a semiconductor memory integrated circuit. As shown in this figure, the input buffer has input terminal to receive the input address signal, an output terminal to send the latched address signal. Moreover, the an input buffer means is connected to an external voltage source to prevent malfunction in case of input signal having excessive level.
However, in the above-mentioned input buffer, the processing speed and the signal robustness is degraded when the voltage level of the external voltage source E.sub.VCC is reduced, for example, from 5V to 3V. Moreover, the output high level V.sub.OH and the noise margin of the input buffer 1 is also degraded such that the output signal thereof may be at a wrong level with respect to next stage circuit.